In the field of Very Large Scale Integration (VLSI) design, a circuit may include, for example, millions or billions of transistors, resistors, capacitors, and various other electrical components. Such components are typically interconnected, for example, on one or more semiconductor “chips”, in order to perform one or more functions. Detecting and rectifying logical errors in a circuit design may be difficult, time-consuming and effort-consuming.
Some methods, based on Binary Decision Diagram (BDD) building, focus on extracting a functional behavior from a circuit by computing “micro-latch” pull-up and pull-down functions for each storage node in the circuit, and by building a transition relation of these functions. These methods may have limited capacity; building a transition relation of an entire sequential circuit may be inefficient and may require significant memory capacity or storage capacity.
Other methods are based on pattern-matching, and may use graph isomorphism algorithms to identify circuit configurations based on a pre-defined set of circuit patterns, for example, domino logic or latches. These methods may be limited or inefficient, since they may not cover all the possible configurations in a circuit. In some methods, user intervention may be required, for example, to enrich the pre-defined pattern set, or to add hints and attributes to help identify unresolved circuit configurations.
Another method tries to analyze a Metal-Oxide-Silicon (MOS) circuit using graph algorithms, by extracting functional behavior of Channel Connected Sub-Networks (CCSNs) using a Gaussian elimination procedure. However, this method focuses on unit delay analysis, and may not be applicable to analyzing and extracting a Register-Transfer (RT) level model.
These methods may suffer from various problems, for example, inefficiency problems and capacity limitations. Some of these problems may be partially mitigated by partitioning a circuit, but this may also be inefficient, time-consuming, and prone to errors.
There is a need for a powerful solution to analyze a circuit, extract its logic behavior, detect errors and resolve wrong or unsafe circuit implementations. There is also a need to generate gate-level or RT-level circuit representation, for example, for further verification against a Hardware Description Language (HDL) specification, for efficient timing or power analysis, for Automatic Test Pattern Generation (ATPG) simulation, for fault grading simulations, or to be used by a suitable VLSI Computer Aided Design (CAD) tool that may operate on switch level models
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.